The present invention relates to integrated circuit technology and, in particular, to techniques for dealing with the injection of carriers into an integrated circuit substrate due to the operation of parasitic devices.
Designers of integrated circuits are familiar with the problems associated with signal levels which go outside the range of supply voltages. These issues are particularly relevant to devices which include power transistors intended to drive inductive loads. For example, in devices having N-type diffusions in a P-type substrate, whenever a signal, e.g., an output signal connected to an N-type diffusion, goes sufficiently below the most negative supply associated with the device, the PN junction associated with the diffusion begins to conduct, resulting in the injection of minority carriers, i.e., electrons, into the substrate.
This is undesirable in that the PN junction of one diffusion may form part of a parasitic transistor with the PN junction of any other N-type diffusion in the device. That is, any other; N-type diffusion can become the collector of a parasitic NPN transistor. When this occurs, the carrier injection caused by the first diffusion results in current being drawn through the parasitic transistor from circuitry in the second diffusion. This can result in the enabling of circuitry associated with the second diffusion at undesirable times. It can also rob current from the circuitry associated with the other diffusions. In situations where the first diffusion is a power transistor with operating current measured in amps, the second diffusion includes control circuitry with operating current measured in microamps, and the beta of the parasitic device is high, the problem is clear.
On the other hand, if the signal exceeds the most positive power supply, a parasitic PNP transistor with the substrate as the collector may be formed resulting in the injection of majority carriers, i.e., holes, into the substrate. Due to the inherent resistivity of semiconductor substrates, this local injection of current tends to raise the local potential of the substrate which may result in the well known and destructive thyristor latch up mechanism.
It is therefore desirable to provide techniques and mechanisms by which the issues associated with the undesirable injection of carriers into integrated circuit substrates are avoided.
According to the present invention, the injection of minority carriers into an integrated circuit substrate is inhibited by allowing local regions of the substrate near certain devices to float rather than having them tied to a fixed potential. According to a more specific embodiment, barrier regions are provided between different portions of a monolithic integrated circuit, e.g., between two power devices, or between a power device and drive circuitry. These barrier regions include a barrier transistor which is connected to local regions of the substrate around the barrier region which are allowed to float within certain bounds, i.e., are not connected to a fixed potential. The local floating regions of the substrate and the barrier transistors operate to inhibit the operation of parasitic devices associated with the power device(s).
According to a particular embodiment, the invention provides an integrated circuit having a substrate, a power transistor in a first region of the substrate, and a plurality of barrier regions of the substrate around the first region. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor.
According to a more specific embodiment, the invention provides an integrated circuit having a substrate, a high-side power transistor in a first region of the substrate, a low-side power transistor in a second region of the substrate, and a plurality of barrier regions of the substrate adjacent and separating the first and second regions. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the high-side and low-side power transistors.
According to yet another embodiment, the present invention provides an integrated circuit having a substrate, a power transistor in a first region of the substrate which is isolated from the substrate by a PN junction, and a locally floating region of the substrate adjacent the first region. During operation of the integrated circuit, the potential of the locally floating region inhibits injection of minority carriers into the substrate due to forward biasing of the PN junction.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.